The present invention relates to correction of faulted memory using spare memory arrays.
In Bond, U.S. patent application Ser. No. 381,266, filed May 24, 1982, now U.S. Pat. No. 4,489,403 issued December 18, 1984, and entitled "Fault Alignment Control System and Circuits", Aichelmann, Jr. et al., U.S. patent application Ser. No. 429,644, filed Sept. 30, 1982, now U.S. Pat. No. 4,506,364 issued Mar. 19, 1985, and entitled "Memory Address Permutation Apparatus", Bossen et al., U.S. patent application Ser. No. 362,925, filed Mar. 29, 1982, now U.S. Pat. No. 4,461,001 issued July 17, 1984, and entitled "Deterministic Permutation Apparatus " and Singh et al., U.S. patent application Ser. No. 383,640, filed June 1, 1982, now U.S. Pat. No. 4,485,471 issued Nov. 27, 1984, and entitled "A Method of Fault Map Generation for Fault Tolerant Memory", the addresses supplied to the decoders of the memory elements storing the various bit positions of a codeword are skewed relative to one another when an uncorrectable error condition is detected in the codeword to change which memory cells store the faulted codeword. This scheme separates stuck bits which caused the uncorrectable error so that they cause correctable error conditions only. For instance, if the memory was protected with a single error correcting code/double error detecting code, the two cells storing the faulted bits of the codeword cntaining a detectable error would be placed so that they occur in two separate codewords where the four would produce two separate correctable error conditions.
While such relocation schemes maintain memory availability, the available memory space becomes "dirty " as a result of the accumulation of bad bits within the space as time passes. This problem is particularly acute where the failed bits are grouped in a completely bad memory chip or are the result of a plurality of bit line or word line fails. Furthermore, with address permutation schemes when a detectable uncorrectable error is detected the whole memory has to be flushed of data while the address skewing process is being performed resulting in a significant down time for the memory.
It has been suggested that memories contain spare arrays which would be used to replace any bad bit in the memory. In one such memory, the location of bad bits are stored separately and whenever memory access is made to an address containing an error, a bit from one of the spare arrays is substituted for the bad bit on a bit by bit basis. While this arrangement ends the accumulation of bad bits in the memory it results in significant increase in the access time of the memory. To get around this problem, it has been suggested that element substitution be done on a column or row basis as in Choate, U.S. Pat. No. 4,051,354, Harper, U.S. Pat. No. 3,633,175, Chesley, U.S. Pat. No. 4,038,648 and Goldberge, U.S. Pat. No. 3,995,261. This involves use of whole spare rows or columns of chips which is quite an inefficient way to use spare memory capacity.